The MPLS WG Archive

[Dillikar Satyanarayana-G19471 <satya@motorola.com>]

Hi JL,
  Thanks for your explanation. As the hardware data-plane branch capability is not known to CSPF Path-Computation-Engine(PCE). PCE only has to rely on E-bit and B-bit of the nodes.
  PCE computing trees T1 and T2 based on given R3 bit status. Please tell us  which tree is valid and which tree is not valid and why?
 
Tree T1: Ingress = R1 Egresses = R2,R3
 
      R1
      |
  R2--R3
 
R3(E=1, B=0)


Tree T2: Ingress = R1 Egresses = R2,R3
 
      R1
      |
  R2--R3
 
R3(E=1, B=1)

TIA,
Satya 

> -----Original Message-----
> From: mpls-bounces@lists.ietf.org 
> [mailto:mpls-bounces@lists.ietf.org] On Behalf Of LE ROUX 
> Jean-Louis RD-CORE-LAN
> Sent: Friday, October 08, 2004 3:57 AM
> To: Satyanarayana Dillikar; mpls@ietf.org; mpls-ops@mplsrc.com
> Cc: ccamp@ops.ietf.org
> Subject: RE : [mpls] 
> draft-vasseur-ccamp-te-router-info-00.txt clarificationneeded.
> 
> 
> Hi Dillikar,
> 
> Sorry for this delayed answer.
> Thanks for these useful comments, that will help clarifying 
> this spec. Please see inline. Regards,
> 
> JL
> 
> PS: I'm copying ccamp
> 
> >-----Message d'origine-----
> >De : mpls-bounces@lists.ietf.org
> >[mailto:mpls-bounces@lists.ietf.org] De la part de 
> >Satyanarayana Dillikar
> >Envoyé : mercredi 6 octobre 2004 10:38
> >À : mpls@ietf.org; mpls-ops@mplsrc.com
> >Objet : [mpls] draft-vasseur-ccamp-te-router-info-00.txt 
> >clarificationneeded.
> >
> >
> >Hi,
> > We have some confusion in understanding the Data
> >Plane Capability Flags (B-bit & E-bit) from
> >draft-vasseur-ccamp-te-router-info-00.txt
> >
> >(a) Does E-bit ON implies B-bit ON always ? (assuming
> >ON = set and OFF = unset).
> 
> Basically bud (transit + Egress) capability requires some 
> branching in the data plane so in general E ON will imply B 
> ON, but note that these capabilities does not necessarily 
> reflect real hardware capabilities as they may be 
> activated/deactivated by the operator for various reasons. We 
> will clarify this point in next revision.
> 
> 
> >(b) E-bit = ON & B-bit = OFF, is it a valid
> >combination.
> 
> Yes see above, there may be cases where the operator want to 
> deactivate branch capability on a node (He does't want that 
> the node act as a branch LSR), even if its data plane is 
> physically branch capable, but he allows the node to act as a 
> bud-LSR (transit + egress). This gives more operational flexibility.
> 
> >(c) Please tell us the E-bit and B-bit status for a
> >node which is a destination node but does not have
> >branch capability.
> 
> If its data plane is not branch capable then it will also 
> probably not be bud capable so 
> E = 0 and B = 0
> 
> In return, if its data plane is branch capable but branch LSR 
> capability has been deactivated by configuration and bud-LSR 
> capability is activated, then E = 1 and B = 0
> 
> >
> >
> >We are also curious to know
> >(1)The idea behind combing two things (egress status &
> >transit status) in a single E-bit. rather than making
> >use of B-bit(branch) and having E-bit just for egress
> >status.
> 
> Remind that these capabilities are used for tree computation 
> purpose, and the egress is an entry 
> of the computation. So, IMHO it does't really make any sense 
> to advertise egress capability only. 
> 
> >(2) Why the TE Node Capability Descriptor TLV should
> >have E-bit & how it should be used in CSPF path
> >computation.
> 
> This allows advertising if an LSR can be transit and egress. 
> This is particulary useful for steiner tree topologies. 
> See the following example: 
> Tree T: Ingress = R1 Egresses = R2, R3, R4
> 
>      R1
>      |
>  R2--R3---R4
> 
> Such tree can be setup only if R3 has Egress + Transit capability.
> 
> 
> Regards,
> 
> JL
> 
> 
> 
> >
> >Thanks
> >Satya
> >
> >
> >		
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